rov-without-earlydepthstencil
Status: stub. The full-length analysis is queued for a v1.0.x patch release per ADR 0018, section 5, criterion #6. The companion rule page at docs/rules/rov-without-earlydepthstencil.md contains the canonical detection logic + GPU reasoning.
TL;DR
ROVs enforce ordering between pixel shader invocations that cover the same pixel: later-rasterized primitives must not commit their ROV writes until earlier-rasterized primitives have completed. On AMD RDNA 2/RDNA 3 and NVIDIA Turing/Ada Lovelace, this ordering is implemented via a serialization primitive — typically a per-pixel lock or a per-pixel write-order fence — that the hardware acquires before any ROV access and releases after. The critical section is the span of shader code between the lock acquisition and the lock release.
What the rule fires on
A pixel shader entry point that declares one or more RasterizerOrderedBuffer<T>, RasterizerOrderedTexture2D<T>, or any other RasterizerOrdered* resource (ROV) without the [earlydepthstencil] function attribute, and without a discard statement or a SV_Depth write that would make early depth legally ambiguous. The rule uses Slang's reflection API to identify entry points with ROV-typed resource bindings and checks whether the [earlydepthstencil] attribute is present. It does not fire when the shader contains discard, writes SV_Depth, or writes SV_Coverage — situations where [earlydepthstencil] would change semantics.
See the What it detects section of the rule page for the full pattern definition.
Why it matters
The full GPU-mechanism analysis lives in the Why it matters on a GPU section of the companion rule page.
Examples
The bad / good code snippets are kept canonical on the rule page; see rov-without-earlydepthstencil.md -> Examples.
See also
- Rule page -- canonical reference + change log.
- bindings overview -- broader context.
- ADR 0018 -- v1.0 readiness plan.
This is a v1.0-ship stub. Full analysis pending; track issue link TBD.